1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to phase change memory devices and related programming methods.
A claim of priority is made to Korean Patent Application No. 10-2006-0033305 filed on Apr. 12, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device—phase change random access memory (PRAM)—uses the amorphous state to represent a logical “1” and the crystalline state to represent a logical “0”. In a PRAM device, the crystalline state is referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical “0” by “setting” a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical “1” by “resetting” the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material (See, e.g., curve “1” in FIG. 3). The phase change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a period of time (See, e.g., curve “2” in FIG. 3). Accordingly, data is written to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling.
The memory cells in a PRAM are called “phase change memory cells”. At least one type of phase change memory cell comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor or a diode, wherein the chalcogenide is the phase change material of the memory cell. Accordingly, a read operation is performed on the phase change memory cell by measuring the resistance of the chalcogenide layer, and a write operation is performed on the phase change memory cell by heating and cooling the chalcogenide layer as described above.
FIG. 1 is a circuit diagram illustrating a conventional phase change memory cell 10. Referring to FIG. 1, memory cell 10 includes a phase change resistance element 11 (also labeled “GST”) comprising the GST compound, and a negative metal-oxide semiconductor (NMOS) transistor 12 (also labeled “NT”). Phase change resistance element 11 is connected between a bit line BL and NMOS transistor 12, and NMOS transistor 12 is connected between phase change resistance element 11 and ground. In addition, NMOS transistor 12 has a gate connected to a word line WL.
NMOS transistor 12 is turned on in response to a word line voltage applied to word line WL. Where NMOS transistor 12 is turned on, phase change resistance element 11 receives a current through bit line BL. Although phase change resistance element 11 is connected between bit line BL and NMOS transistor 12 in FIG. 1, phase change resistance element 11 could alternatively be connected between NMOS transistor 12 and ground.
FIG. 2 illustrates a conventional diode type phase change memory cell 20. Referring to FIG. 2, memory cell 20 comprises a phase change resistance element 21 (also labeled “GST”) connected to a bitline BL, and a diode 22 (also labeled “D”) connected between phase change resistance element 21 and a wordline WL.
Phase change memory cell 20 is accessed by selecting wordline WL and bitline BL. In order for phase change memory cell 20 to work properly, wordline WL must have a lower voltage level than bitline BL when wordline WL is selected so that current can flow through phase change resistance element 21. Diode 22 is forward biased so that if wordline WL has a higher voltage than bitline BL, no current flows through phase change resistance element 21. To ensure that wordline WL has a lower voltage level than bitline BL, wordline WL is generally connected to ground when selected.
In FIGS. 1 and 2, phase change resistance elements 11 and 21 can alternatively be broadly referred to as “memory elements” and NMOS transistor 12 and diode 22 can alternatively be broadly referred to as “select elements”.
The operation of phase change memory cells 10 and 20 is described below with reference to FIG. 3. In particular, FIG. 3 is a graph illustrating temperature characteristics of phase change resistance elements 11 and 21 during programming operations of memory cells 10 and 20. In FIG. 3, a reference numeral “1” denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the amorphous state, and a reference numeral “2” denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the crystalline state.
Referring to FIG. 3, in a transition to the amorphous state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for a duration T1 to increase the temperature of the GST compound above a melting temperature Tm. After duration T1, the temperature of the GST compound is rapidly decreased, or “quenched”, and the GST compound assumes the amorphous state. On the other hand, in a transition to the crystalline state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for an interval T2 (T2>T1) to increase the temperature of the GST compound above a crystallization temperature Tc (Tc <Tm) for a desired period of time. After interval T2, the GST compound is slowly cooled down below the crystallization temperature so that it assumes the crystalline state.
A phase change memory device typically comprises a plurality of phase change memory cells arranged in a memory cell array. Within the memory cell array, each of the memory cells is typically connected to a corresponding bit line and a corresponding word line. For example, the memory cell array may comprise bit lines arranged in columns and word lines arranged in rows, with a phase change memory cell located near each intersection between a column and a row.
Typically, a row of phase change memory cells connected to a particular word line are selected by applying an appropriate voltage level to the particular word line. For example, to select a row of phase change memory cells similar to phase change memory cell 10 illustrated in FIG. 1, a relatively high voltage level is applied to a corresponding word line WL to turn on NMOS transistor 12. Alternatively, to select a row of phase change memory cells similar to phase change memory cell 20 illustrated in FIG. 2, a relatively low voltage level is applied to a corresponding word line WL so that current can flow through diode 22.
Unfortunately, where a programming current is simultaneously applied to the plurality of memory cells connected with one word line, a voltage level of the word line may undesirably increase due to parasitic resistance and parasitic capacitance in the word line. As the voltage level of the word line increases, programming characteristics of the plurality of memory cells may deteriorate. For example, in the diode type phase change memory cell of FIG. 2, if the voltage level of word line WL increases undesirably, diode 22 may not completely turn on.